kontroller Project Status (11/09/2010 - 18:03:25)
Project File: prosjekt.xise Parser Errors: No Errors
Module Name: kontroller Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
23 Warnings (22 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 177 9,312 1%  
Number of 4 input LUTs 1,072 9,312 11%  
Number of occupied Slices 820 4,656 17%  
    Number of Slices containing only related logic 820 820 100%  
    Number of Slices containing unrelated logic 0 820 0%  
Total Number of 4 input LUTs 1,464 9,312 15%  
    Number used as logic 1,072      
    Number used as a route-thru 392      
Number of bonded IOBs 52 232 22%  
Number of BUFGMUXs 3 24 12%  
Average Fanout of Non-Clock Nets 2.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentfr 19. nov 12:19:48 2010023 Warnings (22 new)1 Info (0 new)
Translation ReportCurrentfr 19. nov 12:19:58 2010000
Map ReportCurrentfr 19. nov 12:20:10 2010001 Info (0 new)
Place and Route ReportCurrentfr 19. nov 12:20:48 2010004 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentfr 19. nov 12:20:54 2010005 Infos (0 new)
Bitgen ReportCurrentfr 19. nov 12:21:00 2010000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datefr 12. nov 16:57:58 2010
WebTalk ReportCurrentfr 19. nov 12:21:00 2010
WebTalk Log FileCurrentfr 19. nov 12:21:08 2010

Date Generated: 11/26/2010 - 10:13:19