Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/baud_rate_tb |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=Schematic |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2010-09-29T19:38:23 |
PROP_intWbtProjectID=1DE6EE7B553F43E1A95408D6927906CD |
PROP_intWbtProjectIteration=88 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.baud_rate_tb |
PROP_AutoTop=false |
PROP_CompxlibEdkSimLib=false |
PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s500e |
PROP_DevFamilyPMName=spartan3e |
PROP_ISimSimulationRunTime_behav_tb=1500000 ns |
PROP_DevPackage=fg320 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=VHDL |
FILE_SCHEMATIC=2 |
FILE_UCF=1 |
FILE_VHDL=16 |